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AMIS-42665 High-Speed Low Power CAN Transceiver
Description
The AMIS-42665 CAN transceiver is the interface between a controller area network (CAN) protocol controller and the physical bus and may be used in both 12 V and 24 V systems. The transceiver provides differential transmit capability to the bus and differential receive capability to the CAN controller. Due to the wide common-mode voltage range of the receiver inputs, the AMIS-42665 is able to reach outstanding levels of electromagnetic susceptibility (EMS). Similarly, extremely low electromagnetic emission (EME) is achieved by the excellent matching of the output signals. The AMIS-42665 is a new addition to the CAN high-speed transceiver family and offers the following additional features:
Features
http://onsemi.com MARKING DIAGRAM
8 8 1 XXXXX A L Y W G SOIC-8 CASE 751 1 XXXXX ALYW G
* Wake-up (WU) Over Bus * Voltage Source via VSPLIT Pin for Stabilizing the Recessive Bus * * * * * * * * * * * * * * *
= Specific Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb-Free Package
Level (Further EMC Improvement) Ideal Passive Behavior when Supply Voltage is Removed Extremely Low Current Standby Mode Compatible with the ISO 11898 Standard (ISO 11898-2, ISO 11898-5 and SAE J2284) High Speed (up to 1 Mbps) Ideally Suited for 12 V and 24 V Industrial and Automotive Applications Extremely Low Current Standby Mode with Wake-up via the Bus Low EME Common-Mode Choke is No Longer Required Differential Receiver with Wide Common-Mode Range ($35 V) for High EMS Transmit Data (TxD) Dominant Time-out Function Thermal Protection Bus Pins Protected against Transients in an Automotive Environment Power Down Mode in which the Transmitter is Disabled Bus and VSPLIT Pins Short Circuit Proof to Supply Voltage and Ground Logic Level Inputs Compatible with 3.3 V Devices These are Pb-Free Devices
PIN ASSIGNMENT
TxD GND VCC RxD
1 2 3 4
8 7 6 5
STB CANH CANL VSPLIT
(Top View)
ORDERING INFORMATION
See detailed ordering and shipping information in the package dimensions section on page 10 of this data sheet.
AMIS- 42665
PC20040829.1
(c) Semiconductor Components Industries, LLC, 2010
April, 2010 - Rev. 8
1
Publication Order Number: AMIS-42665/D
AMIS-42665
Table 1. TECHNICAL CHARACTERISTICS
Symbol VCC VSTB VTxD VRxD VCANH VCANL VSPLIT VO(dif)(bus_dom) CM-range VCM-peak Cload tpd(rec-dom) tpd(dom-rec) TJ Parameter Power Supply Voltage DC Voltage at Pin STB DC Voltage at Pin TxD DC Voltage at Pin RxD DC Voltage at Pin CANH DC Voltage at Pin CANL DC Voltage at Pin VSPLIT Differential Bus Output Voltage in Dominant State Input Common-Mode Range for Comparator Common-Mode Peak Load Capacitance on IC Outputs Propagation Delay TxD to RxD Propagation Delay TxD to RxD Junction Temperature
VCC 3 VCC AMIS-42665 POR 7 1 TxD VCC Timer Thermal Shutdown VCC VSPLIT 5 VSPLIT CANH
Conditions
Min 4.75 -0.3 -0.3 -0.3
Max 5.25 VCC VCC VCC +35 +35 +35 3 +35 500 10
Unit V V V V V V V V V mV pF ns ns C
0 < VCC < 5.25 V; No Time Limit 0 < VCC < 5.25 V; No Time Limit 0 < VCC < 5.25 V; No Time Limit 42.5 W < RLT < 60 W Guaranteed Differential Receiver Threshold and Leakage Current See Figures 11 and 12
-35 -35 -35 1.5 -35 -500
See Figure 7 See Figure 7
90 90 -40
230 245 150
8 STB
Mode & Wake-up Control
Driver Control
6 CANL
4 RxD
Wake-up Filter
+ COMP - + COMP -
GND
2
Figure 1. Block Diagram
PC20050211.1
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AMIS-42665
TYPICAL APPLICATION
VBAT
IN
5V-reg
OUT VCC STB 8 3 7 CANH
VCC RLT = 60 W
CAN Controller
RxD 4
AMIS- 42665
VSPLIT 5
CLT = 47 nF
CAN BUS
TxD 1 2 GND PC20040829.3 GND
6
CANL R
Figure 2. Application Diagram
Table 2. PIN LIST AND DESCRIPTIONS
Pin 1 2 3 4 5 6 7 8 Name TxD GND VCC RxD VSPLIT CANL CANH STB Description Transmit Data Input; Low Input Dominant Driver; Internal Pullup Current Ground Supply Voltage Receive Data Output; Dominant transmitter Low Output Common-Mode Stabilization Output Low-Level CAN Bus Line (Low in Dominant Mode) High-Level CAN Bus Line (High in Dominant Mode) Standby Mode Control Input
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Table 3. ABSOLUTE MAXIMUM RATINGS
Symbol VCC VCANH VCANL VSPLIT VTxD VRxD VSTB Vtran(CANH) Vtran(CANL) Vtran(VSPLIT) Vesd(CANL/
CANH/VSPLIT)
Parameter Supply Voltage DC Voltage at Pin CANH DC Voltage at Pin CANL DC Voltage at Pin VSPLIT DC Voltage at Pin TxD DC Voltage at Pin RxD DC Voltage at Pin STB Transient Voltage at Pin CANH Transient voltage at Pin CANL Transient Voltage at Pin VSPLIT Electrostatic Discharge Voltage at CANH and CANL Pin Electrostatic Discharge Voltage at All Other Pins Static Latch-up at all Pins Storage Temperature Ambient Temperature Maximum Junction Temperature Note 1 Note 1 Note 1 Note 2 Note 4 Note 2 Note 4 Note 3
Conditions
Min. -0.3
Max. +7 +50 +50 +50 VCC + 0.3 VCC + 0.3 VCC + 0.3 +300 +300 +300 +8 +500 +5 +500 120
Unit V V V V V V V V V V kV V kV V mA C C C
0 < VCC < 5.25 V; No Time Limit 0 < VCC < 5.25 V; No Time Limit 0 < VCC < 5.25 V; No Time Limit
-50 -50 -50 -0.3 -0.3 -0.3 -300 -300 -300 -8 -500 -5 -500
Vesd Latch-up Tstg Tamb TJ
-55 -40 -40
+150 +125 +170
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. Applied transient waveforms in accordance with ISO 7637 part 3, test pulses 1, 2, 3a, and 3b (see Figure 5). 2. Standardized human body model electrostatic discharge (ESD) pulses in accordance to MIL883 method 3015.7. 3. Static latch-up immunity: Static latch-up protection level when tested according to EIA/JESD78. 4. Standardized charged device model ESD pulses when tested according to EOS/ESD DS5.3-1993.
Table 4. THERMAL CHARACTERISTICS
Symbol Rth(vj-a) Rth(vj-s) Parameter Thermal Resistance from Junction-to-Ambient in SOIC-8 Package Thermal Resistance from Junction-to-Substrate of Bare Die Conditions In free air In free air Value 145 45 Unit K/W K/W
FUNCTIONAL DESCRIPTION AMIS-42665 provides two modes of operation as illustrated in Table 5. These modes are selectable through pin STB.
Table 5. OPERATING MODES
Pin RXD Mode Normal Standby Pin STB Low High Low Bus Dominant Wake-up Request Detected High Bus Recessive No Wake-up Request Detected
Normal Mode
Standby Mode
In the normal mode, the transceiver is able to communicate via the bus lines. The signals are transmitted and received to the CAN controller via the pins TxD and RxD. The slopes on the bus lines outputs are optimized to give extremely low EME.
In standby mode both the transmitter and receiver are disabled and a very low-power differential receiver monitors the bus lines for CAN bus activity. The bus lines are terminated to ground and supply current is reduced to a minimum, typically 10 mA. When a wake-up request is
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AMIS-42665
detected by the low-power differential receiver, the signal is first filtered and then verified as a valid wake signal after a time period of tdbus, the RxD pin is driven low by the transceiver to inform the controller of the wake-up request.
Split Circuit Overtemperature Detection
The VSPLIT Pin is operational only in normal mode. In standby mode this pin is floating. The VSPLIT is connected as shown in Figure 2 and its purpose is to provide a stabilized DC voltage of 0.5 x VCC to the bus avoiding possible steps in the common-mode signal therefore reducing EME. These unwanted steps could be caused by an unpowered node on the network with excessive leakage current from the bus that shifts the recessive voltage from its nominal 0.5 x VCC voltage.
Wake-up
A thermal protection circuit protects the IC from damage by switching off the transmitter if the junction temperature exceeds a value of approximately 160C. Because the transmitter dissipates most of the power, the power dissipation and temperature of the IC is reduced. All other IC functions continue to operate. The transmitter off-state resets when Pin TxD goes high. The thermal protection circuit is particularly needed when a bus line short circuits.
TxD Dominant Time-out Function
When a valid wake-up (dominant state longer than tdbus) is received during the standby mode the RxD pin is driven low. Wake-up behavior in case of a permanent dominant - due to, for example, a bus short - represents the only difference between the circuit sub-versions listed in the Ordering Information table. It is depicted in Figures 3 and 4. When the standby mode is entered while a dominant is present on the bus, the "unconditioned bus wake-up" versions will signal a bus-wakeup immediately after the state transition (seen as a High-level glitch on RxD). The other version (differing purely by a metal-level modification in the digital part) will signal bus-wakeup only after the initial dominant is released. In this way it's ensured, that a CAN bus can be put to a low-power mode even if the nodes have a level sensitivity to RxD pin and a permanent dominant is present on the bus.
A TxD dominant time-out timer circuit prevents the bus lines being driven to a permanent dominant state (blocking all network communication) if Pin TxD is forced permanently low by a hardware and/or software application failure. The timer is triggered by a negative edge on pin TxD. If the duration of the low-level on Pin TxD exceeds the internal timer value tdom(TxD), the transmitter is disabled, driving the bus into a recessive state. The timer is reset by a positive edge on Pin TxD. See Figure 10. This TxD dominant time-out time (tdom(TxD)) defines the minimum possible bit rate to 40 kbps.
Fail Safe Features
A current-limiting circuit protects the transmitter output stage from damage caused by accidental short circuit to either positive or negative supply voltage, although power dissipation increases during this fault condition. The pins CANH and CANL are protected from automotive electrical transients (according to ISO 7637; see Figure 5). Pins TxD and STB are pulled high internally should the input become disconnected. Pins TxD, STB and RxD will be floating, preventing reverse supply should the VCC supply be removed.
tdbus tdbus
CANH CANL
STB RxD unconditioned WU Normal Standby* time
*Even if bus dominant signals longer than tdbus are echoed on RxD, the transceiver stays in standby mode until STB is released.
Figure 3. AMIS42665TJAA1/3 Wake-up Behavior
CANH CANL
tdbus
STB RxD
Normal
Standby*
time
*On this derivative, bus dominant signals longer than tdbus are echoed on RxD after the bus passed through a recessive time following the trigtger of STB. The transceiver stays in standby mode until STB is released.
Figure 4. AMIS42665TJAA6 Wake-up Behavior http://onsemi.com
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AMIS-42665
ELECTRICAL CHARACTERISTICS
Definitions
All voltages are referenced to GND (Pin 2). Positive currents flow into the IC. Sinking current means the current
is flowing into the pin; sourcing current means the current is flowing out of the pin.
CHARACTERISTICS VCC = 4.75 V to 5.25 V; TJ = -40C to +150C; RLT = 60 W unless specified otherwise.
Symbol SUPPLY (PIN VCC) ICC ICCS VIH VIL IIH IIL Ci VIH VIL IIH IIL Ci Ioh Iol Vo(reces) (norm) Vo(reces) (stby) Io(reces) (CANH) Io(reces) (CANL) ILI(CANH) ILI(CANL) Vo(dom) (CANH) Vo(dom) (CANL) Vo(dif) (bus_dom) Vo(dif) (bus_rec) Io(sc) (CANH) Supply Current Supply Current in Standby Mode Dominant; VTxD = 0 V Recessive; VTxD = VCC TJ,max = 100C Output Recessive Output Dominant VTxD = VCC VTxD = 0 V Not Tested 2.0 -0.3 -5 -75 - 45 4 10 65 8 15 mA mA Parameter Conditions Min Typ Max Unit
TRANSMITTER DATA INPUT (PIN TxD) High-Level Input Voltage Low-Level Input Voltage High-Level Input Current Low-Level Input Current Input Capacitance - - 0 -200 5 VCC + 0.3 +0.8 +5 -350 10 V V mA mA pF
TRANSMITTER MODE SELECT (PIN STB) High-Level Input Voltage Low-Level Input Voltage High-Level Input Current Low-Level Input Current Input Capacitance Standby Mode Normal Mode VSTB = VCC VSTB = 0 V Not Tested 2.0 -0.3 -5 -1 - - - 0 -4 5 VCC + 0.3 +0.8 +5 -10 10 V V mA mA pF
RECEIVER DATA OUTPUT (PIN RxD) High-Level Output Current Low-Level Output Current Vo = 0.7 x VCC Vo = 0.3 x VCC VTxD = VCC; No Load VTxD = VCC; No Load Standby Mode -35 V < VCANH < +35 V; 0 V < VCC < 5.25 V -35 V < VCANL < +35 V; 0 V < VCC < 5.25 V VCC = 0 V; VCANL = VCANH = 5 V VCC = 0 V; VCANL = VCANH = 5 V VTxD = 0 V VTxD = 0 V VTxD = 0 V; Dominant; 42.5 W < RLT < 60 W VTxD = VCC; Recessive; No Load VCANH = 0 V; VTxD = 0 V -5 5 -10 10 -15 15 mA mA
BUS LINES (PINS CANH AND CANL) Recessive Bus Voltage Normal Mode Recessive Bus Voltage Recessive Output Current at Pin CANH Recessive Output Current at Pin CANL Input Leakage Current to Pin CANH Input Leakage Current to Pin CANL Dominant Output Voltage at Pin CANH Dominant Output Voltage at Pin CANL Differential Bus Output Voltage (VCANH - VCANL) Differential Bus Output Voltage (VCANH - VCANL) Short Circuit Output Current at Pin CANH 2.0 -100 -2.5 -2.5 -10 -10 3.0 0. 5 1.5 -120 -45 2.5 0 - - - - 3.6 1.4 2.25 0 -70 3.0 100 +2.5 +2.5 +10 +10 4.25 1.75 3.0 +50 -120 V mV mA mA mA mA V V V mV mA
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CHARACTERISTICS VCC = 4.75 V to 5.25 V; TJ = -40C to +150C; RLT = 60 W unless specified otherwise.
Symbol Parameter Conditions Min Typ Max Unit BUS LINES (PINS CANH AND CANL) Io(sc) (CANL) Vi(dif) (th) Vihcm(dif) (th) Vi(dif) (hys) Ri(cm) (CANH) Ri(cm) (CANL) Ri(cm) (m) Ri(dif) Ci(CANH) Ci(CANL) Ci(dif) VSPLIT ISPLIT(i) ISPLIT(lim) PORL Short Circuit Output Current at Pin CANL Differential Receiver Threshold Voltage (see Figure 6) Differential Receiver Threshold Voltage for High Common-Mode (See Figure 6) Differential Receiver Input Voltage Hysteresis (see Figure 6) Common-Mode Input Resistance at Pin CANH Common-Mode Input Resistance at Pin CANL Matching Between Pin CANH and Pin CANL Common Mode Input Resistance Differential Input Resistance Input Capacitance at Pin CANH Input Capacitance at Pin CANL Differential Input Capacitance VTxD = VCC; Not Tested VTxD = VCC; Not Tested VTxD = VCC; Not Tested Normal Mode; -500 mA < ISPLIT < 500 mA Standby Mode Normal Mode 0.3 x VCC -5 -3 VCANH = VCANL VCANL = 36 V; VTxD = 0 V -5 V < VCANL < +12 V; -5 V < VCANH < +12 V; -35 V < VCANL < +35 V; -35 V < VCANH < +35 V; -35 V < VCANL < +35 V; -35 V < VCANH < +35 V; 45 0.5 0.40 50 15 15 -3 25 70 0.7 0.7 70 26 26 0 50 7.5 7.5 3.75 120 0.9 1.00 100 37 37 +3 75 20 20 10 mA V V mV kW kW % kW pF pF pF
COMMON-MODE STABILIZATION (PIN VSPLIT) Reference Output Voltage at Pin VSPLIT VSPLIT Leakage Current VSPLIT Limitation Current POR Level - 0.7 x VCC +5 +3 mA mA
POWER-ON-RESET (POR) CANH, CANL, Vref in Tri-State Below POR Level 2.2 3.5 4.7 V
THERMAL SHUTDOWN TJ(sd) td(TxD-BUSon) td(TxD-BUSoff) td(BUSon-RXD) td(BUSoff-RXD) tpd(rec-dom) td(dom-rec) td(stb-nm) tdbus tdom(TxD) Baudrate Shutdown Junction Temperature 150 160 180 C
TIMING CHARACTERISTICS (see Figures 7 and 8) Delay TXD to Bus Active Delay TXD to Bus Inactive Delay Bus Active to RXD Delay Bus Inactive to RXD Propagation Delay TXD to RXD from Recessive-to-Dominant Propagation Delay TXD to RXD from Dominant-to-Recessive Delay Standby Mode to Normal Mode Dominant Time for Wake-up via Bus TxD Dominant Time for Time Out Communication Speed Achievable VTxD = 0 V Cl = 100 pF Between CANH to CANL Cl = 100 pF Between CANH to CANL Crxd = 15 pF Crxd = 15 pF Cl = 100 pF Between CANH to CANL Cl = 100 pF Between CANH to CANL 40 30 25 40 90 90 5 0.75 300 40k 7.5 2.5 650 85 60 55 100 105 105 105 105 230 245 10 5 1000 1M ns ns ns ns ns ns ms ms ms bps
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MEASUREMENT SETUPS AND DEFINITIONS
+5 V 100 nF VCC 3 7 1 AMIS- 42665 RxD 4 6 8 15 pF STB GND 2 CANL VSPLIT 5 CANH 1 nF
TxD
Transient Generator
1 nF PC20040829.5
Figure 5. Test Circuit for Automotive Transients
VRxD High
Low
Hysteresis PC20040829.7 0.5 0.9 Vi(dif)(hys)
Figure 6. Hysteresis of the Receiver
+5 V 100 nF VCC 3 7 1 AMIS- 42665 VSPLIT 5 60 W RxD 4 6 CANL 8 15 pF STB 2 GND PC20040829.4 100 pF RLT CLT CANH
TxD
Figure 7. : Test Circuit for Timing Characteristics
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AMIS-42665
HIGH TxD LOW
CANH
CANL
Vi(dif) = VCANH - VCANL
0.9 V 0.5 V
Dominant
RxD
Recessive
0.3 x VCC Td(TxD-BUSon) Td(TxD-BUSoff)
0.7 x VCC
Td(BUSoff-RxD) Tpd(rec-dom) Tpd(dom-rec) PC20040829.6
Figure 8. Timing Diagram for AC Characteristics
td(stb-nm) STB Standby Normal Transition delay time
Mode
Figure 9. Transition from Standby to Normal
td(stb-nm) TxD CANH CANL *The time-out is reset on TxD rising edge. time Time-Out(*)
Figure 10. AMIS-42665 TxD Time-Out Bus Blockage Prevention in Case of Controller Failure
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+5 V 100 nF 3 TxD 1 AMIS- 42665 RxD CANL 6.2 kW Spectrum Anayzer 30 W 5 VSPLIT 8 15 pF STB 2 GND 47 nF 30 W 7 CANH VCC 6.2 kW 10 nF Active Probe 6
Generator
4
Figure 11. Basic Test Setup for Electromagnetic Measurement
PC20040829.9
Figure 12. EME Measurements
DEVICE ORDERING INFORMATION
Part Number AMIS42665TJAA1G AMIS42665TJAA1RG AMIS42665TJAA3L AMIS42665TJAA3RL AMIS42665TJAA6G AMIS42665TJAA6RG Bus Wake-up Inactive in Case of Bus Fault Version Unconditioned Bus Wake-up Temperature Range -40C - 125C -40C - 125C -40C - 125C -40C - 125C -40C - 125C -40C - 125C Package Type SOIC-8* (Pb-Free) SOIC-8* (Pb-Free) SOIC-8** (Pb-Free) SOIC-8** (Pb-Free) SOIC-8* (Pb-Free) SOIC-8* (Pb-Free) Shipping 96 Tube / Tray 3000 / Tape & Reel 96 Tube / Tray 3000 / Tape & Reel 96 Tube / Tray 3000 / Tape & Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *Matte Sn, JEDEC MS-012 ** NiPdAu, JEDEC MS-012
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PACKAGE DIMENSIONS
SOIC-8 CASE 751-07 ISSUE AJ
-X-
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. 751-01 THRU 751-06 ARE OBSOLETE. NEW STANDARD IS 751-07. DIM A B C D G H J K M N S MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 BSC 0.10 0.25 0.19 0.25 0.40 1.27 0_ 8_ 0.25 0.50 5.80 6.20 INCHES MIN MAX 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 BSC 0.004 0.010 0.007 0.010 0.016 0.050 0_ 8_ 0.010 0.020 0.228 0.244
A
8 5
B
1
S
4
0.25 (0.010)
M
Y
M
-Y- G
K
C -Z- H D 0.25 (0.010)
M SEATING PLANE
N
X 45 _
0.10 (0.004)
M
J
ZY
S
X
S
SOLDERING FOOTPRINT*
1.52 0.060
7.0 0.275
4.0 0.155
0.6 0.024
1.270 0.050
SCALE 6:1 mm inches
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 800-282-9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81-3-5773-3850 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative
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AMIS-42665/D

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